1. Technical Field
Example embodiments of the invention relate to stacked ferroelectric memory devices, methods of manufacturing the stacked ferroelectric memory devices, ferroelectric memory circuits and methods of driving the ferroelectric memory circuits. More particularly, example embodiments of the invention relate to stacked ferroelectric memory devices in which a random access operation is available and data is quickly readable without destroying data, methods of manufacturing the stacked ferroelectric memory devices, ferroelectric memory circuits in which a random access operation is available and data is quickly readable without destroying data, and methods of driving the ferroelectric memory circuits.
2. Description of the Related Art
Recently, various kinds of non-volatile memory devices have been studied as a next-generation memory device for replacing dynamic random access memory (DRAM) devices. The non-volatile memory devices have been studied with a goal of achieving a high storage capacity, a high response speed and a low power consumption architecture. Examples of the next-generation memory devices are magnetic random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, etc. The FRAM devices have an advantage that data in the FRAM devices is not volatile. Additionally, the FRAM devices have other advantages such as a high processing speed and a low power consumption architecture, which make the FRAM devices desirable for further research.
The FRAM devices have a ferroelectric transistor or a ferroelectric capacitor including a ferroelectric material serving as a memory, or storage, member in a unit cell. The ferroelectric material has hysteretic characteristics due to its spontaneous polarization. The unit cell of the FRAM devices may be implemented to have various structures such as a 1T1C structure consisting of one selection transistor and one capacitor or a 2T2C structure consisting of two selection transistors and two capacitors. Additionally, the unit cell of the FRAM devices may have a 1T structure consisting of one selection transistor.
When the FRAM devices have a unit cell of the 1T1C structure or the 2T2C structure, the FRAM devices perform a destructive readout (DRO) operation and a write-back operation after reading data, thereby slowing down the speed of reading data. Additionally, at least one transistor and one capacitor are needed in the unit cell so that an area occupied by the unit cell may be increased relative to other structures.
When the FRAM devices have a unit cell of the 1T structure, data may be determined by a fluctuation in the size of the drain current flowing in a channel region of the transistor that varies according to the polarization direction of a ferroelectric layer used as a gate insulation layer. The FRAM devices having the unit cell of the 1T structure may read data without destroying data, i.e., the FRAM devices perform a non-destructive readout (NDRO) operation so that reading data may be completed very quickly. Additionally, the degree of integration may be increased relative to other structures because only one ferroelectric transistor is needed in the unit cell. However, the FRAM devices having the unit cell of the 1T structure may have a significant disadvantage over other structures in that a read/write operation is performed by pages or blocks because a random access operation is not available in the above FRAM devices.
Therefore, there have been demands for non-volatile memory devices which are capable of performing a fast reading operation and a random access operation, i.e., an operation that selectively reads/writes data on a selected address, and also have a high degree of integration.